A plasma display panel is a matrix type screen or panel formed by cells positioned at the intersections of rows and columns. A cell has a cavity filled with a rare gas, two control electrodes and a deposit of red, green or blue phosphorus. To create a light dot on the screen using a given cell, a potential difference is applied between the control electrodes of this cell to activate an ionization of the gas. This ionization is accompanied by an emission of ultraviolet rays. The creation of the light dot is obtained by the excitation of the deposited phosphorus by the emitted rays.
The cells are classically activated to create images by logic circuits producing control signals. The logic states of these signals determine the cells that are commanded to produce a light dot and the cells that are commanded not to produce any light dots. The logic circuits are generally powered at low voltage, for example a voltage of 5V or less. This voltage is not sufficient to directly drive the electrodes of the cells. Between the logic circuits and the cells to be controlled, power output stages are therefore used to convert the low-voltage control signals into high-voltage control signals.
The ionization of the gas of the cavities requires the application of high potentials for the control electrodes, in the range of about 100V. Furthermore, it is necessary to be able to provide the electrodes with high currents, in the range of several tens of milliamperes (and also to be able to receive these currents from these electrodes). Indeed, the electrodes may be represented schematically by equivalent capacitors having relatively high capacitance values of about 100 picofarads. The controlling of the electrodes is therefore equivalent to the control implemented for charging or discharging a capacitor.
In plasma display panels, it is generally desired to obtain signals (current and voltage signals) that have steep edges. This represents for example charging or discharging times of about 100 nanoseconds. Given the high potential to be attained and the size of the capacitive charge, this entails the assumption that it is possible to provide very high charging currents and absorb very high discharge currents that could go up to about 100 milliamperes.
A high-potential output stage receives a low-voltage logic signal at input, having its low state for example at 0V and its high state VDD typically at about 3 to 5V, and, at output, provides a control signal OUT to charge or discharge a load coupled to its output. The signal OUT is a high-voltage signal, typically in the range of 50 to 120V. In the case of a plasma display panel, the load is a cell of the panel which, from an electrical viewpoint, behaves like a capacitive load.
A high-potential output stage of this kind can work in two different modes: a mode known as a “direct” mode (the DC mode) and a mode called the “alternating” mode (AC mode).
In the DC mode, the high power supply potential is set at a value VPP-DC and is equal to the high state of the high-voltage logic. A change in state of the low-voltage input signal entails a change in state of the high-potential output signal.
In the AC mode, the power supply potential VPP-AC is equal to 0V for a half period and is variable during another half period: VPP-AC does a build-up, for example from 0V to VPP-DC in 200 nanoseconds, and then gets stabilized at this high value, for example for 400 nanoseconds, and then falls back to 0V, for example in 200 nanoseconds. If the input signal is in an active state (for example in the low state), then the potential of the output signal OUT is supposed to follow the variations of the potential VPP-AC. If, on the contrary, the input signal is in an inactive state (for example in the high state), the output potential OUT remains in the low state.
The passage of the potential of the output signal from the low state to the high state is produced by the charging of the output capacitor through a transistor.
In DC mode, this transistor works in saturation during almost the entire change in state. This leads to high dissipation in this transistor. In AC mode, it is sought to make this transistor work in ohmic conduction in order to limit the dissipation in the transistor. The AC mode therefore has the advantage of reducing the dissipation of the system as compared with the DC mode.
Here below, only circuits working in AC mode shall be dealt with.
A prior-art high-potential output stage is shown in FIG. 1. It includes a level shifter circuit 10, a control circuit 20, and an output circuit 30. The output stage powers a load Cout, represented in FIG. 1 by a capacitor. The output stage is powered by the high potential VPP-AC produced by an oscillator 40 from the DC power supply VPP-DC. Depending on the input signal IN, the output stage gives a signal OUT to the load Cout.
The level shifter 10 amplifies the input logic signal IN and produces a signal INP such that:                if IN=0, INP=0        if IN=VDD, INP=VPP-AC.        
The circuit 30 has an N type, high-voltage output transistor T31 equipped with a Zener diode D33 antiparallel-mounted between the gate and the source of T31. The transistor T31 has an intrinsic diode D34 antiparallel-connected between its drain and its source. The circuit 30 also has another high-voltage N type transistor T32 coupled between the source of the transistor T31 and a ground terminal VSS. The common node of the transistors T31, T32 forms the output of the output stage, at which the signal OUT is produced.
The level shifter 10 and the control circuit 20 together form a driving circuit of the output circuit 30; the circuit 20 is formed by a high-voltage P type transistor T21 and a high-voltage N type transistor T22. T21, T22 are series-connected, the drain of T21 receiving the potential VPP-AC and the source of T22 being ground-connected. Starting from the signal INP applied to the gate of T21 and the signal IN applied to the gate of T22, this circuit 20 produces a control signal INH at the common drain of the transistors T21, T22. This control signal INH is applied to the gate of the output transistor T31. INH turns the transistor T31 on or off; INH depends on IN and on VPP-AC.
When the transistor T31 is activated by the signal INH, the output signal OUT follows the variations of the signal VPP-AC:                when VPP-AC rises, a charging current flows from the oscillator 40 to the load Cout through the transistor T31, to charge the load Cout and accordingly increase the potential OUT: T31 works in ohmic conduction, at least at the end of charging,        when VPP-AC is constant at VPP-DC, OUT is constant and equal to VPP-DC−VT, VT being a potential threshold of T31,        when VPP-AC decreases, a discharge current flows from the load Cout to the oscillator 40 through the diode. D34 of the transistor T31, to discharge the load Cout and reduce the potential OUT accordingly.        
The overall working of the output stage in FIG. 1 is described in detail in the document D1 (US20040012411) or in the priority document FR2840468.
This output stage nevertheless has one drawback: T31 works in saturation at the beginning of the charging due to the high conduction threshold of the transistor T21 (in the range of 10V).
Indeed, so long as VPP-AC has not reached 10V, T21 is not conductive and INH remains at 0V, hence T31 is not conductive. When VPP-AC=10V, T21 is conductive and INH starts rising. When INH reaches a conduction threshold of T31 (in the range of 1.5V), T31 starts rising and the output builds up. However T31 is conductive with a high voltage (>10V) between its drain (VPP-AC) and its source (the output). Transistor T31 is therefore conductive in saturation. This results in substantial dissipation of power in the transistor T31, and that is detrimental.
However, as soon as the output has reached VPP-AC (in fact, setting aside Vds=Vgs, Vds and Vgs being respectively the drain/source voltage and the gate/source voltage of T31), T31 works in ohmic conduction and the dissipation is limited.
Document D1 proposes a solution to this problem. The solution comprises adding a control transistor parallel-connected to the transistor T21, between the drain and the gate of T31, and sized to have a low conduction threshold of about 1.5V. Thus, the transistor T31 starts conducting before VPP-AC reaches 10V; it therefore works very little in saturation, thus limiting the dissipated energy.
However, the dissipation remains as yet non-negligible. Furthermore, there is a risk of simultaneous conduction of the added control transistor and of the transistor T32 when the signal OUT is at the low level. This results in an additional dissipation of energy.